1. Field of the Invention
The present invention relates to a random access semiconductor memory, more particularly to an electrically erasable programmable nonvolatile semiconductor memory device such as a flash memory.
2. Description of the Related Art
At the present time, flash memories are coming under attention as low cost, large capacity EEPROMs. Attempts are being made to realize ones of 16 Mbits. Further, improvements are being made so that instead of the complete erasure as in the past, erasure of specific sectors is made possible to thereby further increase the ease of use.
Flash memories, however, have a remarkably longer erasure time and write time compared with the speed of the CPU to restrict excess erasure and excess writing in addition to basic factors of writing/erasure.
At the present time, it takes 0.1 to 2 seconds for erasing 1 Mbit and 0.2 second/16 KB for writing.
A flash memory as a semiconductor memory device ideally should have no erasure operation and should be able to perform writing at a speed commensurate with the speed of the CPU like with an SRAM.
Also, a flash memory is limited in the number of rewriting. The number of rewriting in the current art is about 10.sup.6 at a maximum. From the application standpoint, however, there is a demand for use up to 10.sup.6 to 10.sup.9 times since even part of the capacity of the flash memory is enough.
As explained above, a flash memory has a slow rewriting speed and a durability of the number of rewriting of about 10.sup.4 to 10.sup.5.
Accordingly, in the past, there has been proposed a nonvolatile RAM (NVRAM) comprised of an SRAM (or DRAM) and an EEPROM, coupled one-to-one in each memory cell unit, which has the contents of the SRAM or DRAM written in the EEPROM in accordance with need.
Further, as a semiconductor nonvolatile memory device achieving both a higher speed of the write operation and a nonvolatile nature without the use of a battery, as disclosed for example in Japanese Unexamined Patent Publication (Kokai) No. 4-176091, there is known a device provided with a flash EEPROM as a nonvolatile memory device, a DRAM as a volatile memory device, a control circuit for making the contents of the two memory devices match in accordance with an external signal, an internal address bus electrically isolated from an external address bus by a signal from the control circuit, and an internal data bus also electrically isolated from the external data bus by a signal from the control circuit.
In this semiconductor nonvolatile memory device, data is transferred from the flash EEPROM to the DRAM when the device is first assembled into the processing unit. Normal reading and writing are performed with respect to the DRAM. Upon instruction from the CPU, the contents of the DRAM are cached in the flash EEPROM.
The conventional NVRAM, however, was comprised of an SRAM (or DRAM) and EEPROM coupled one-to-one in memory cell units, so became larger in size than the sum of the size of a simple DRAM (or DRAM) cell and size of an EEPROM cell. Due to costs and other problems, further, realization of a larger capacity was difficult.
Further, in the semiconductor nonvolatile memory device disclosed in Japanese Unexamined Patent Publication No. 4-176091, the flash EEPROM and DRAM are formed on different chips, so viewing the device as a whole, the write and erasure times of the flash EEPROM are slow and the timing of the writing and erasure and designation of commands become complicated.